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High Performance Onboard Multicore Architecture for RPAS Avionics

Employ high performance hardware architectures for RPAS missions.

Objective

Employ high performance hardware architectures on UAS based missions to verify real-time operability of small surveillance platforms via the use of on-board multicore (36 cores) processor technology.

 

Demonstrate the UAS flight-plan / mission management interaction with the high performance architecture to exploit sensor data on-board the UAS.

 

Permit high-level of surveillance dynamics and flexibility according to the actual stream of data being sensed.

 


Above it is shown the general architecture of the UAS-tailored IPM module as projected.

Box Design and Integration CAD and Fabrication


Helicopter supports:

  • Easy removal.

    No damage to elastomers.

    General purpose for future payload.

    Ultralightweight avionics box.

    Tailored to the inch.






 




Upper view of the box Prototype

 

In this figure is shown the upper view of the first high performance avionics box ready to be installed  in the Remotely Piloted Aircraft Systems.

 


 


 

 

 

 

 

 


Botton view of the box Prototype


 

In this figure is shown the botton view of the high performance avionics box. Main CPU and Tilera Multicore (36 cores) board are connected to the Ethrnet Switch to develop the RPAS civil missions.










RPAS Configuration with the High Performance Onboard Multicore

First Test successful!!!!




















Next Step:

Copterworks AF25B Integration